1. Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to the implementation transaction flow control techniques.
2. Description of the Related Art
Computing systems may include one or more systems on a chip (SoC), which may integrate a number of different functions, such as, graphics processing, onto a single integrated circuit. With numerous functions included in a single integrated circuit, chip count may be kept low in mobile computing systems, such as tablets, for example, which may result in reduced assembly costs, and a smaller form factor for such mobile computing systems.
Each functional block included within an SoC may be designed in accordance to one of various design flows. The logical operation of some functional blocks may be described in a high-level computer language such as, e.g., Very-high-speed integrated circuit hardware description language (VHDL). Logic gate implementations of blocks described in such a fashion may be generated using logic synthesis and place-and-route design techniques. Other functional blocks, such as memories, phase-locked loops (PLLs), analog-to-digital converters (ADCs), may be designed in a full-custom fashion.
Functional blocks within an SoC may be connected to one another through a bus. Such busses may employ proprietary communications protocols or they may employ industry-standard communication protocols, such as, Peripheral Component Interconnect Express (PCIe®), for example. Some SoC implementations may allow for multiple communication protocols to be employed between the various functional blocks included within the SoC. The transfer of transactions, i.e., requests and responses, may be sent over a communication bus. In some designs, flow control techniques may be employed to limit or prevent stall situations from occurring during the transfer of transactions.
In some SoC designs, multiple clock signals may be employed allowing different functional blocks within an SoC to operate at different frequencies, and allowing clock signals to be stopped for a given functional block when the block's functionality is not required. Asynchronous first in first out (FIFO) buffers or registers may be employed in some designs to aid in the transfer of transactions between two functional blocks operating at two different clock frequencies.